HBM
Direct Answer
HBM (High Bandwidth Memory), standardized by JEDEC in October 2013, takes a fundamentally different approach from GDDR -- stacking multiple DRAM dies vertically and connecting them via through-silicon vias next to the GPU on a silicon interposer, trading GDDR's narrower, faster-clocked bus for a much wider, slower one. Manufacturing cost has kept it mostly in high-end compute GPUs rather than mainstream cards.
Source: JEDEC JESD235
Specs
| JEDEC Standard | October 2013 (JESD235) |
| Architecture | Vertically stacked DRAM dies, through-silicon vias (TSVs), silicon interposer |
| Bus Width (4-Hi Stack) | 1024-bit (8 x 128-bit channels) |
| Typical Use | High-end compute/datacenter GPUs, not mainstream consumer cards |
A Wider, Slower Bus Built by Stacking
HBM takes an architecturally different approach from GDDR: rather than mounting memory chips flat on the circuit board around the GPU, HBM stacks multiple DRAM dies vertically, connecting them with through-silicon vias (TSVs) that pass signals straight through each die, and mounts the whole stack immediately next to the GPU die on a shared silicon interposer. A typical 4-die-high stack provides two 128-bit channels per die -- eight channels and 1024 bits of total bus width, dramatically wider than any single GDDR chip's 32-bit bus, but clocked far more conservatively to manage power and heat in that dense, stacked arrangement.
JEDEC standardized HBM as JESD235 in October 2013, with SK Hynix producing the first HBM chips that year. The interposer-and-TSV manufacturing process is considerably more expensive than mounting standard GDDR chips on a PCB, which has kept HBM concentrated in high-end compute-class GPUs and accelerators rather than mainstream consumer graphics cards, where GDDR's lower cost remains the better fit.