HBM3
Direct Answer
HBM3, announced by JEDEC in January 2022, doubled channel count to 16 within the same 1024-bit bus width and reaches roughly 819 GB/s of bandwidth per stack. It's used predominantly in AI and datacenter accelerators like Nvidia's H100, rather than consumer graphics cards.
Source: JEDEC
Specs
| JEDEC Standard | January 2022 |
| Channels | 16 x 64-bit (1024-bit total bus, same as HBM2) |
| Bandwidth | ~819 GB/s per stack |
| Primary Use | AI/datacenter accelerators |
Built for AI Accelerators
JEDEC announced the HBM3 standard on January 27, 2022, doubling channel count to 16 independent 64-bit channels while keeping the same 1024-bit total bus width as HBM2, alongside higher per-pin speeds -- SK Hynix's implementation reached 6.4 Gbit/s per pin, pushing bandwidth to roughly 819 GB/s per stack.
HBM3's dominant use case is AI and datacenter accelerators -- Nvidia's H100 is a widely-cited example -- rather than consumer graphics cards, continuing the pattern set by earlier HBM generations of going where the cost of stacked, interposer-mounted memory is easiest to justify. A further HBM3E extension followed in 2023 with roughly 1 TB/s per stack, continuing the same trajectory.